Flip chip packages include a semiconductor die mounted onto a package substrate with the active side of the die facing the substrate. The substrate is made up of a dielectric layer and at least one metal layer, patterned to provide substrate circuitry, which includes among other features traces (“leads”) leading to interconnect pads. The metal layer may be patterned by, for example, a mask-and etch process. Conventionally, interconnection of the circuitry in the die with circuitry in the substrate is made by way of bumps which are attached to an array of interconnect pads on the die, and bonded to a corresponding (complementary) array of interconnect pads (often referred to as “capture pads”) on the substrate. The capture pads are typically much wider than the leads, and can be as wide as, for example, about 2 to 4 times the nominal or design width of the leads.
The areal density of electronic features on integrated circuits has increased enormously, and chips having a greater density of circuit features also may have a greater density of sites (“die pads”) for interconnection with the circuitry on a package substrate.
The package is connected to underlying circuitry, such as a printed circuit board (e.g., a “motherboard”), in the device in which the package is employed, by way of second level interconnects (e.g., pins, secondary interconnect solder balls) between the package and the underlying circuit. The second level interconnects have a greater pitch than the flip chip interconnects, and so the routing on the substrate conventionally “fans out”. Significant technological advances in patterning the metal layer on the substrate have enabled construction of fine lines and spaces; but in the conventional arrangement space between adjacent pads limits the number of traces than can escape from the more inward capture pads in the array, and the fan out routing between the capture pads beneath the die and the external pins of the package is conventionally formed on multiple metal layers within the package substrate. For a complex interconnect array, substrates having multiple layers may be required to achieve routing between the die pads and the second level interconnects on the package.
Multiple layer substrates are expensive, and in conventional flip chip constructs the substrate alone typically accounts for more than half the package cost (about 60% in some typical instances). The high cost of multilayer substrates has been a factor in limiting proliferation of flip chip technology in mainstream products.
In conventional flip chip constructs the escape routing pattern typically introduces additional electrical parasitics, because the routing includes short runs of unshielded wiring and vias between wiring layers in the signal transmission path. Electrical parasitics can significantly limit package performance.